![]() The signal done indicates that the computation is done. ![]() The module SQRTLOG computes four functions according to the signal op as can be seen below: ![]() In order to show the synthesis process of an IP-Core, the block SQRTLOG depicted in the Figure (2) will be used as an example. Figure (1): Synopsys Design Compiler basic tool flow Learning from an example The outputs generated by the Design Compiler are the Gate Level Netlist (the synthesized RTL), sdc constraints and also reports about estimated area, power and the timing of the netlist. It has as inputs the design file (Verilog, VHDL or SystemVerilog), the Standard Cell library (a database file format which is the de facto industry standard for data exchange of integrated circuit or IC layout atwork) and the commands to execute the tool during the synthesis process (scripts in tcl). In the Figure (1) can be seen the basic tool flow of the Design Compiler. The Design Compiler from Synopsys is a tool that fits well in the hardware synthesis and this tutorial will show briefly how it can be used for this purpose. During this process the RTL code (normally described in the behavorial logic) should be translated into a gate level netlist. ![]() One of the most important steps of the ASIC design flow is the RTL to GDSII implementation.
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